Semiconductor devices, such as application specific integrated circuits ("ASIC's"), are thoroughly tested to ensure proper performance before being shipped to a customer. Automatic test pattern generating ("ATPG") tools are used to generate test patterns, or vectors, necessary to test the devices. Generally, a semiconductor device is designed with either a schematic design tool, which allows transistor level design, or a synthesis tool which allows a circuit to be designed from various modules which are linked into and accessible by the tool. In either case, the resulting design data is then supplied to an ATPG tool. The ATPG tool also receives input from a script file which contains various commands, such as conditioning for inputs, which inform the tool of the various conditions and states for which the device is to be tested.
From these inputs, the ATPG tool then generates the test vectors which will be used by automatic test equipment ("ATE") to test the device. Suitable ATE is well known in the art and examples include wafer probing equipment such as the ST212 manufactured by Creedence Systems, Inc. The ATE then tests the device by supplying the test vectors generated by the ATPG tool to the inputs of the device and recording the outputs of the device in response. The outputs generated by the device should match the outputs predicted by logic simulation of the design. If not, then the device may be considered defective and disposed of.
Generally, the vectors are chosen to test the transistors in the device in both the on and off state. While complete coverage of all the transistors in the device is not always obtainable, it is still desirable to test at least a high percentage of them. However, there are other types of defects which can occur in the device which are not necessarily detectable by vectors which are designed for checking transistor states. For example, short circuits can occur between two wires which are adjacent on the chip. This type of defect is referred to as a "bridge fault" and may escape undetected by present automatic test pattern generators because ATPG tools are typically not provided with information about the physical location of the wires on the device and, consequently, are unable to generate appropriate test vectors. It is therefore, one object of the present invention to provide a method for testing for bridge faults in semiconductor devices. Further objects and advantages will become apparent in view of the following disclosure.